Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.
